Pvt stable voltage regulator

ABSTRACT

An apparatus includes a voltage regulation module configured to provide an output voltage signal (Vout) and an auto-calibration module configured to provide a calibration current signal (Isink) corresponding to a voltage difference between a target voltage signal (Vtarget) and the output voltage signal (Vout). The voltage regulation module may adjust the output voltage in response to changes in the calibration current signal. In one embodiment, the voltage regulation module comprises an output voltage resistor pair of resistance R1 and R2, respectively, and the output voltage signal conforms to the equation Vout=Isink·R1+Vref·(1+R1/R2).

BACKGROUND OF THE INVENTION

The present invention relates generally to electronic circuits such asintegrated circuits, and more particularly to voltage regulators in suchcircuits.

Voltage regulators, particularly low-dropout voltage regulators,typically use digital calibration engines to tune the regulators andaccount for process, voltage, and temperature (PVT) related variationsin the regulated output voltage. Despite the foregoing, an extreme PVTcondition may place a FET driver on the regulator output in a deeplinear region of operation instead of the desired saturation region.Operating in a deep linear region results significant PVT sensitivityand poor voltage regulation.

SUMMARY

An apparatus includes a voltage regulation module configured to providean output voltage signal (Vout) and an auto-calibration moduleconfigured to provide a calibration current signal (Isink) correspondingto a voltage difference between a target voltage signal (Vtarget) andthe output voltage signal (Vout). The voltage regulation module mayadjust the output voltage in response to changes in the calibrationcurrent signal. In one embodiment, the voltage regulation modulecomprises an output voltage resistor pair of resistance R1 and R2,respectively, and the output voltage signal conforms to the equationVout=Isink·R1+Vref·(1+R1/R2).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram depicting one example of a voltage regulationsystem in accordance with at least one embodiment of the presentinvention;

FIG. 2 is schematic diagram of one example of an auto-calibration modulein accordance with at least one embodiment of the present invention;

FIG. 3 is schematic diagram depicting one example of the voltageregulation module and the auto-calibration module of FIG. 1 in greaterdetail; and

FIG. 4 is a graph that illustrates the effect of auto-calibration onregulation stability.

DETAILED DESCRIPTION

At least some of the embodiments disclosed herein recognize thatband-gap based voltage references are not available with many processtechnologies due to non-availability of bipolar devices. Also as supplyvoltages drop below 1 volt, FET-based reference circuits are used forbiasing voltage regulators. Unfortunately, FET-based voltage referencesvary widely against process (P), voltage (V) and temperature (T)(collectively PVT) variations resulting in large variations in theoutput voltage of regulators—particularly low drop-out voltageregulators that are needed on integrated circuits.

To address this situation, digital calibration engines are used toadjust the relationship between the voltage reference input and theregulated output voltage. However, digital calibration engines consumesignificant chip area and power during calibration and typically canonly be adjusted at system initialization. Furthermore, digitalcalibration complicates the start-up and initialization process of thechip and may fail to calibrate the regulated output at process, voltage,and temperature extremes.

It should be noted that references throughout this specification tofeatures, advantages, or similar language herein do not imply that allof the features and advantages that may be realized with the embodimentsdisclosed herein should be, or are in, any single embodiment of theinvention. Rather, language referring to the features and advantages isunderstood to mean that a specific feature, advantage, or characteristicdescribed in connection with an embodiment is included in at least oneembodiment of the present invention. Thus, discussion of the features,advantages, and similar language, throughout this specification may, butdo not necessarily, refer to the same embodiment.

Furthermore, the described features, advantages, and characteristics ofthe invention may be combined in any suitable manner in one or moreembodiments. One skilled in the relevant art will recognize that theinvention may be practiced without one or more of the specific featuresor advantages of a particular embodiment. In other instances, additionalfeatures and advantages may be recognized in certain embodiments thatmay not be present in all embodiments of the invention. These featuresand advantages will become more fully apparent from the followingdrawings, description and appended claims, or may be learned by thepractice of the invention as set forth hereinafter.

FIG. 1 is a block diagram depicting one example of a voltage regulationsystem 100 in accordance with at least one embodiment of the presentinvention. As depicted, the voltage regulation system 100 includes avoltage reference module 110, a voltage regulation module 120, anauto-calibration module 130, and a voltage divider 140. The voltageregulation system 100 provides stable voltage regulation despite varyingPVT conditions. In some embodiments, the voltage regulation system 100provides on-chip voltage regulation.

The voltage reference module 110 provides a voltage reference Vref tothe voltage regulation module 120. The voltage reference Vref may be aFET-based reference that varies significantly under varying PVTconditions but provides a high power supply rejection ratio (PSRR). Thevoltage regulation module 120 receives the voltage reference Vref and acalibration current (Isink) and provides an output voltage Vout. In someembodiments, the voltage regulation module includes a voltage multipliercircuit that multiplies Vref by a selected ratio. In addition, thevoltage regulation module may receive the calibration current Isink thatcalibrates the voltage regulation module and adjusts for PVT variationsin the voltage reference Vref.

The auto-calibration module 130 receives the output voltage Vout and atarget voltage Vtarget and provides the calibration current Isink. Inthe depicted embodiment, Isink corresponds to (e.g., is proportional to)a voltage difference between Vtarget and Vout. Vtarget may be a targetvoltage that is highly stable across PVT variations but has a low PSRR.In some embodiments, Vtarget is substantially equal to the desiredvoltage for Vout. In the depicted embodiment, Vtarget is provided by avoltage divider 140 that is driven by a supply voltage Vsupply resultingin high PVT stability but a low PSRR.

FIG. 2 is schematic diagram of one example of an auto-calibration module200 in accordance with at least one embodiment of the present invention.As depicted, the auto-calibration module 200 includes an amplifier 210that drives a pull-down transistor 220. The auto-calibration module 200provides a calibration current Isink that corresponds to a differencebetween the output voltage Vout and the target voltage Vtarget. In thedepicted embodiment, the amplifier 210 is an operationaltransconductance amplifier that includes an op amp 212 and a pair ofvoltage controlled current sources 214. The auto-calibration module 200is one example of the auto-calibration module 130 shown in FIG. 1.

FIG. 3 is schematic diagram depicting one example of the voltageregulation module 120 and the auto-calibration module 130 of FIG. 1 ingreater detail. As depicted, the auto-calibration module 130 includes apair of differential input transistors (Q3, Q4) driven by Vout andVtarget respectively, which produce differential currents I3 and I4which are mirrored by the mirroring transistors Q5-Q8 resulting in avoltage Vsink that varies according to the voltage difference betweenVout and Vtarget. The voltage Vsink drives the current sink transistorQ11 resulting in the calibration current Isink. The calibration currentIsink provides an alternate current path for the current flowing throughthe output resistor R1 and effectively changes Vout by an amountequivalent to Isink*R1 as internal voltage signal Vint equalizes withVref during regulation. Consequently, the gain provided by the voltageregulation module 120 and the resulting output voltage Vout can beadjusted by the auto-calibration module 130 via the calibration currentIsink. In the depicted embodiment, the voltage regulation module 120increases the output voltage in response to an increase in calibrationcurrent signal Isink and reduces the output voltage in response to adecrease in the calibration current signal Isink. In the depictedembodiment, the output voltage signal conforms to the equationVout=Isink·R1+Vref·(1+R1/R2). The voltage regulation module 120 may alsocomprise a compensation network 124 that increases feedback stability.Consequently, the output voltage signal Vout provided by voltageregulation module may be highly insensitive to PVT variations while alsoachieving a high PSRR metric.

FIG. 4 is a graph that illustrates the effect of auto-calibration onregulation stability. Due to PVT variations, the reference voltage Vrefmay vary significantly resulting in variations in Vout. In the depictedexample, the reference voltage Vref varies from 335 mV to 485 mV andVout varies from 520 mV to 730 mV for a variation range of approximately40 percent. However, by activating an auto-calibration module such asthe auto-calibration module 200, Vout is stabilized despite PVTvariations and only varies between 896 and 904 mV corresponding to avariation range of approximately 1 percent. The depicted results are fora c14 (14 nm) process technology.

One of skill in the art will appreciate that at least some of theembodiments disclosed herein eliminate the problem of wide fluctuationof regulator output as VREF changes with variations in PVT. Furthermore,such fluctuations are diminished without using a digital calibrationengine. Additionally, auto-calibration works dynamically andautomatically during chip operation and locks Vout to VTarget even ifVREF changes with changing PVT conditions. Working dynamically andautomatically during chip operation is a benefit that digitallycalibrated voltage regulators are NOT able to achieve as the digitalcalibration algorithms run only during initialization and under RESETconditions. Furthermore, additional complex digital calibrationalgorithms and associated circuits and logic functionalities are notrequired resulting in simplified regulator operation and reduced powerconsumption.

It should be noted that this description is not intended to limit theinvention. On the contrary, the embodiments presented are intended tocover some of the alternatives, modifications, and equivalents, whichare included in the spirit and scope of the invention as defined by theappended claims. Further, in the detailed description of the disclosedembodiments, numerous specific details are set forth in order to providea comprehensive understanding of the claimed invention. However, oneskilled in the art would understand that various embodiments may bepracticed without such specific details.

Although the features and elements of the embodiments disclosed hereinare described in particular combinations, each feature or element can beused alone without the other features and elements of the embodiments orin various combinations with or without other features and elementsdisclosed herein.

This written description uses examples of the subject matter disclosedto enable any person skilled in the art to practice the same, includingmaking and using any devices or systems and performing any incorporatedmethods. The patentable scope of the subject matter is defined by theclaims, and may include other examples that occur to those skilled inthe art. Such other examples are intended to be within the scope of theclaims.

What is claimed is:
 1. A method comprising: generating an output voltagesignal (Vout); providing a voltage reference signal (Vref); generating acalibration current signal (Isink) corresponding to a voltage differencebetween a target voltage signal (Vtarget) derived from a power supplysignal and the output voltage signal (Vout); adjusting the outputvoltage in response to changes in the calibration current signal;wherein adjusting the output voltage comprises increasing the outputvoltage in response to an increase in the calibration current signal andreducing the output voltage in response to a decrease in the calibrationcurrent signal; wherein the calibration current signal is generated bydriving a current sink transistor with an operational transconductanceamplifier; wherein Vout is provided by a voltage regulation modulecomprising a first resistor of resistance R1 and a second resistor ofresistance R2 and Vout conforms to the equationVout=Isink·R1+Vref·(1+R1/R2); wherein Vref is provided by a voltagereference module comprising field-effect transistors (FETs); and whereinVout is substantially equal to the target voltage signal (Vtarget).